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検索結果 4 件

Studies on F-Scan: A Design for Testability Method for Functional RTL Circuits

Studies on F-Scan: A Design for Testability Method for Functional RTL Circuits
デジタル博士論文
Obien, Marie Engelene JimenezNara Institute of Science and Technology2011-03-24
全国の図書館
  • 件名scan-based design for testability functional register transfer ...

Studies on test generation and design for testability based on knowledge for LSIs

Studies on test generation and design for testability based on knowledge for LSIs
デジタル博士論文
中里, 昌人Nara Institute of Science and Technology2007-03-23
全国の図書館
  • 件名...ased self-test design for testability processor testing test knowle...

Studies on power constrained test techniques for VLSI circuits

Studies on power constrained test techniques for VLSI circuits
デジタル博士論文
尤, 志強Nara Institute of Science and Technology2006-03-24
全国の図書館
  • 件名design for testability RTL data path built-in self-t...

Area and time co-optimization for system-on-a-chip based on consecutive testability

Area and time co-optimization for system-on-a-chip based on consecutive testability
デジタル文書・図像類
Yoneda, Tomokazu, Uchiyama, Tetsuo, Fujiwara, HideoNara Institute of Science and Technology2003-02Information Science Technical ReportTR2003002
インターネットで読める全国の図書館
  • 件名system-on-a-chip design for testability test access mechanism test sc...

検索結果は以上です。