年 〜
年

検索結果 3 件

Studies on DFT for reducing its area and test application time of system-on-a-chip

Studies on DFT for reducing its area and test application time of system-on-a-chip
デジタル博士論文
宮崎, 政英Nara Institute of Science and Technology2006-03-24
全国の図書館
  • 件名SoC test scheduling test access mechanism wrapper design for test memor...

An SoC test scheduling algorithm using reconfigurable union wrappers

An SoC test scheduling algorithm using reconfigurable union wrappers
デジタル文書・図像類
Yoneda, Tomokazu, Imanishi, Masahiro, Fujiwara, HideoNara Institute of Science and Technology2006-09Information Science Technical ReportTR2006006
インターネットで読める全国の図書館
  • 件名system-on-a-chip test scheduling reconfigurable union wrapper test access mechanism

Area and time co-optimization for system-on-a-chip based on consecutive testability

Area and time co-optimization for system-on-a-chip based on consecutive testability
デジタル文書・図像類
Yoneda, Tomokazu, Uchiyama, Tetsuo, Fujiwara, HideoNara Institute of Science and Technology2003-02Information Science Technical ReportTR2003002
インターネットで読める全国の図書館
  • 要約等Test access mechanism and test scheduling are integ...
  • 件名...or testability test access mechanism test scheduling consecutive t...

検索結果は以上です。