並列タイトル等FPGA ニヨル ITU-656 ビデオカメラ ノ インターフェイス オヨビ ガゾウ エンザンキ ノ セッケイ
A Design of an Interface and Image Processing Circuit with FPGA for ITU-656 Video Camera
タイトル(掲載誌)愛知工業大学研究報告 = Bulletin of Aichi Institute of Technology
一般注記High-speed processing is necessary to perform image processing in real time. Hardware processing with FPGA is one of the ways to process images fast. A system processing images from video camera in real time has been designed. The system has the following blocks. 1) An interface circuit getting images from camera, de-inter-race and transfer them to SDRAM. 2) An image Processor. Two images read from the SDRAM are processed by subtraction and segmentation to 2 values. Then the resulted image is stored into the SDRAM. The processing speed with the FPGA was enough to perform real-time processing.
identifier:http://repository.aitech.ac.jp/dspace/handle/11133/1415
一次資料へのリンクURLhttp://repository.aitech.ac.jp/dspace/bitstream/11133/1415/1/%e7%b4%80%e8%a6%8143%e5%8f%b7%28P29-34%29.pdf
連携機関・データベース国立情報学研究所 : 学術機関リポジトリデータベース(IRDB)(機関リポジトリ)