並列タイトル等A study of improved jitter performance and reduced spurious stones in digital phase locked loops using ΔΣmodulators.
一般注記type:Thesis
This paper proposes ge neralization of the casca de connection of the digital phase locked loop, application of ΔΣTDC, and application of ΔΣmodulator to reduce PLL jitter.Due to the process down scaling of MOS technology, the power supply voltage will also reduce, making it difficult to design analog rich circuits, ;thus, it is necessary to shift analog phase locked loop (PLL) technique to digital PLL technique. During digitalization, problems have become clear such as quantization error, spurious tones due to reference clock, and characteristic deterioration due to manufacturing variation.In this paper, in order to solve these problems, the authors describe the noise suppression characteristics of the PLL's conventional feedback circuit, and propose a frequency multiplication architecture that does not use DLLs but uses multiple parallel ΔΣTDCs. In addition, we describe not only the circuit design technique but also a method of improving the characteristics of the entire system by combining the shuffling t echnology with the ΔΣmodulator.In this paper, after examining ΔΣTDC exclusively, we describe the improvement of characteristics of the entire digital PLL.
コレクション(個別)国立国会図書館デジタルコレクション > デジタル化資料 > 博士論文
受理日(W3CDTF)2021-07-05T22:24:43+09:00
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