博士論文

ΔΣ変調器を用いたデジタル位相同期ループのジッタ性能改善とスプリアス低減に関する研究

Icons representing 博士論文
The cover of this title could differ from library to library. Link to Help Page

ΔΣ変調器を用いたデジタル位相同期ループのジッタ性能改善とスプリアス低減に関する研究

Persistent ID (NDL)
info:ndljp/pid/11692110
Material type
博士論文
Author
嘉藤, 貴博
Publisher
-
Publication date
2021-03-24
Material Format
Digital
Capacity, size, etc.
-
Name of awarding university/degree
法政大学 (Hosei University),博士(工学)
View All

Notes on use at the National Diet Library

Notes on use

Note (General):

type:ThesisThis paper proposes ge neralization of the casca de connection of the digital phase locked loop, application of ΔΣTDC, and application of Δ...

Table of Contents

  • 2024-02-02 再収集

  • 2024-02-02 再収集

Bibliographic Record

You can check the details of this material, its authority (keywords that refer to materials on the same subject, author's name, etc.), etc.

Digital

Material Type
博士論文
Author/Editor
嘉藤, 貴博
Author Heading
Publication Date
2021-03-24
Publication Date (W3CDTF)
2021-03-24
Alternative Title
A study of improved jitter performance and reduced spurious stones in digital phase locked loops using ΔΣmodulators.
Degree grantor/type
法政大学 (Hosei University)
Date Granted
2021-03-24
Date Granted (W3CDTF)
2021-03-24