マルチチャネルADCを用いたフルディジタル位相雑音計測におけるサンプリングクロックの位相雑音除去量に関する検討 (計測研究会 温度計測及び一般)

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マルチチャネルADCを用いたフルディジタル位相雑音計測におけるサンプリングクロックの位相雑音除去量に関する検討

(計測研究会 温度計測及び一般)

Call No. (NDL)
Z43-232
Bibliographic ID of National Diet Library
030371835
Material type
記事
Author
芹澤 竜己ほか
Publisher
東京 : 電気学会
Publication date
2020-03-27
Material Format
Paper
Journal name
電気学会研究会資料. IM = The papers of technical meeting on instrumentation and measurement, IEE Japan / 計測研究会 [編] 2020(8-16):2020.3.27
Publication Page
p.1-4
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Paper

Material Type
記事
Author/Editor
芹澤 竜己
今池 健
Alternative Title
Study on Phase Noise Rejection Quantity of Sampling Clock in Fully Digital Phase Noise Measurement System using Multi Channel ADCs
Periodical title
電気学会研究会資料. IM = The papers of technical meeting on instrumentation and measurement, IEE Japan / 計測研究会 [編]
No. or year of volume/issue
2020(8-16):2020.3.27
Volume
2020
Issue
8-16