CMOS回路におけるタイミング歩留り最大化のためのゲートサイジング手法の提案
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- Material Type
- 文書・図像類
- Author/Editor
- 坂本, 良太室山, 真徳石原, 亨安浦, 寛人
- Publication, Distribution, etc.
- Publication Date
- 2007-03
- Publication Date (W3CDTF)
- 2007-03
- Alternative Title
- A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits
- Periodical title
- 電子情報通信学会技術研究報告, VLD2006-208
- Pages
- 67-72