VLSIレイアウト設計におけるタイミングドリブン配置・配線アルゴリズムに関する研究

• Material Type: 博士論文
• Title: VLSIレイアウト設計におけるタイミングドリブン配置・配線アルゴリズムに関する研究
• Author/Editor: 小出, 哲士
• Author Heading: 小出, 哲士
• Alternative Title: A Study on Timing-Driven Placement and Routing Algorithms in VLSI Layout Design
• Degree grantor/type: 広島大学
• Date Granted: 1998-01-08
• Dissertation Number: 乙第3033号
• Degree Type: 博士(工学); Engineering
• Text Language Code: eng
• Target Audience: 一般
• DOI: 10.11501/3147815
• Format (IMT): application/pdf
• Source: fulltext; http://ir.lib.hiroshima-u.ac.jp/31920/files/26939
• Access Restrictions: インターネット公開
• Rights (production): Copyright(c) by Author
• Data Provider (Database): 国立情報学研究所 : 学術機関リポジトリデータベース（IRDB）（機関リポジトリ）; https://irdb.nii.ac.jp
• Original Data Provider (Database): 広島大学 : 広島大学学術情報リポジトリ

• Summary, etc.: Advancements in semi-conductor technology has made it possible for VLSI circuits to contain even millions of gates. In addition, we expect VLSI circui...

Table of Contents

Abstract / p5
Acknowledgments / p7
Table of Contents / p9
List of Figures / p13
List of Tables / p17
1 Introduction / p1
　1.1 VLSI Layout Design / p2
　1.2 Timing-Driven Layout Design / p9
　1.3 Goal of the Dissertation / p15
　1.4 Organization of the Dissertation / p17
2 A Timing-Driven Placement Algorithm for Standard Cell Layout / p21
　2.1 Introduction / p21
　2.2 Preliminaries / p24
　2.3 POPINS:A New Timing-Driven Placement Algorithm / p28
　2.4 Extension to a Parallel Algorithm PAR-POPINS / p38
　2.5 Experimental Studies / p41
　2.6 Concluding Remarks / p45
3 A Timing-Driven Global Routing Algorithm for Standard Cell Layout / p47
　3.1 Introduction / p47
　3.2 Preliminaries / p48
　3.3 TD-gR:A New Timing-Driven Global Router / p50
　3.4 Experimental Studies / p63
　3.5 Concluding Remarks / p65
4 Over-the-Cell Channel Routing Algorithms for Standard Cell Layout / p67
　4.1 Introduction / p67
　4.2 New Cell Models for Over-the-Cell Routing / p70
　4.3 Three-Layer Over-the-Cell Routing for the BTM-N / p73
　4.4 Three-Layer Over-the-Cell Multi-Channel Routing for the ATM-O / p81
　4.5 Experimental Studies / p90
　4.6 Concluding Remarks / p94
5 Floorplanning, Global Routing and Pin Assignment Algorithms for Building Block Layout / p97
　5.1 Introduction / p97
　5.2 TD-FPN:A Timing-Driven Floorplanning Algorithm / p100
　5.3 TD-gRPA:A Timing-Driven Global Routing Algorithm with Coarse Pin Assignment, Block Reshaping, and Positioning / p108
　5.4 ACPA1:An Optimal Channel Pin Assignment Algorithm / p116
　5.5 Experimental Studies / p122
　5.6 Concluding Remarks / p132
6 Conclusion / p133
A Details of the Timing-Driven Placement Algorithm in Chapter2 / p137
　A.1 Definitions of the Terminal and Wire Gains / p137
　A.2 Details of the Parallel Algorithm PAR-POPlNS / p138
　A.3 Details of Experimental Results / p143
B A Global Routing Algorithm for Over-the-Cell Channel Routing / p149
　B.1 Preliminaries / p149
　B.2 Overview of the Algorithm gROTC / p150
C Details of the OTC Routing Algorithms in Chapter4 / p153
　C.1 Net Decomposition Methods for 3DR-BTM-N / p153
　C.2 Proof of Theorem 4.1 / p155
　C.3 Transformation from the BTM to the ATM-0 / p156
D Proofs of Lemmas and Theorem for the ACPA1 in Chapter5 / p159