Alternative TitleA study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction
Note (General)In order to avoid CMOS down-scaling limit due to the short-channel effect, multi-gate structure, such as fin-FETs or Tri-gate has been introduced. In addition, MOSFETs with new channel materials such as InGaAs (III-V) and Ge are studied for low power application under low voltage. Also, HEMT (High Electron Mobility Transistor) devices using AlGaN/GaN hetero-junction for the channel are being developed for power and high-frequency applications.For the development of these emerging device technologies, it is important to accurately evaluate the distribution of interface and near-interface traps at the gate dielectrics/semiconductor interfaces and the semiconductor hetero-junction interfaces and thus, to understand the behavior of those traps. In this thesis, the results of the systematic studies for the distribution of interface and near-nterface traps at SiO2/Si interfaces with fin structure, high-k/InGaAs interfaces, and AlGaN/GaN hetero-interfaces are described. We have proposed methodologies for trap characterization and revealed in-depth understanding of the distributions, origins, species, and trapping mechanisms. These methodologies and discoveries can be also easily extended for studying other dielectric/semiconductor interfaces and semiconductor hetero-interfaces, and thus provide a guideline for trap characterization for future development of advanced FETs. In particular, following characterizing methodologies were proposed: (1) extraction of trap densities in the different regions of fin surface by the measurement of trap densities with different fin width, (2) extraction of near-interface traps (or border traps) for high-k/III-V MOS structures, from the C-V characteristics measured at different temperatures, and (3) extraction of the distribution and species of the interface traps by comparative study on conductance spectra of AlGaN/GaN hetero-junctions with different electrodes. The major results are listed as follows; At the SiO2/Si interface with fin structure, a high concentration of interface traps tend to locate at the corners. In high-k/III-V MOS systems, there are a large amount of electrically active oxide border traps, whose concentration is likely to increase with increasing energy level and distance from the interface into the oxide. These traps seem to be caused by accumulated defectives during high-k material growth. Besides, the trapping process of oxide border traps is found to be caused by thermal activation. At last, for AlGaN/GaN hetero-interfaces, it is confirmed that there are no distributed bulk traps in the near interfacial region of the hetero-interface. Besides, the different properties of deep trap levels and shallow trap levels at the hetero-interface are also presented.
identifier:oai:t2r2.star.titech.ac.jp:50231564
Collection (particular)国立国会図書館デジタルコレクション > デジタル化資料 > 博士論文
Date Accepted (W3CDTF)2015-07-01T13:17:09+09:00
Data Provider (Database)国立国会図書館 : 国立国会図書館デジタルコレクション