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Table of Contents
Chapter1 序論
Chapter2 データの表現
Chapter3 演算回路
Chapter4 同期回路
Chapter5 コンピュータの構成と命令実行
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Bibliographic Record
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- Material Type
- 図書
- ISBN
- 978-4-627-85781-0
- Title
- Title Transcription
- ヨク ワカル コンピュータ アーキテクチャ
- Author/Editor
- 鈴木健一 著
- Author Heading
- 著者 ： 鈴木, 健一, 1969- スズキ, ケンイチ, 1969- ( 001210593 )Authorities
- Publication, Distribution, etc.
- Publication Date
- 2024.9
- Publication Date (W3CDTF)
- 2024
- Extent
- 147p