Power reduction in global bus lines in VLSIs
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Table of Contents
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Contents
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1 Introduction
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1.1 Power wiring delay in future VLSIs
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1.2 Target and outline of this dissertation
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Appendix I Power consumption in global wiring in future VLSIs
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- Material Type
- 博士論文
- Author/Editor
- 池田誠 [著]
- Author Heading
- 池田, 誠 イケダ, マコト
- Alternative Title
- 大規模集積回路の大域バス配線における消費電力の削減に関する研究 ダイキボ シュウセキ カイロ ノ タイイキ バス ハイセン ニ オケル ショウヒ デンリョク ノ サクゲン ニ カンスル ケンキュウ
- Degree grantor/type
- 東京大学
- Date Granted
- 平成8年3月29日
- Date Granted (W3CDTF)
- 1996
- Dissertation Number
- 甲第11818号
- Degree Type
- 博士 (工学)