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Search results 89

α-synucleinの凝集・蓄積に関する生化学的解析

α-synucleinの凝集・蓄積に関する生化学的解析
Paper博士論文
藤原英雄 [著][藤原英雄][2004]<UT51-2005-A976>
National Diet Library

Enhanced Functional Fault Model for Micro Operation Faults

Enhanced Functional Fault Model for Micro Operation Faults
Digital文書・図像類
Ooi, Chia Yee, Fujiwara, HideoNara Institute of Science and Technology2010-08Information Science Technical ReportTR2010004
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Fujiwara, Hideo

An Approach to RTL False Path Mapping Using Uniqueness of Paths

An Approach to RTL False Path Mapping Using Uniqueness of Paths
Digital文書・図像類
Iwata, Hiroshi, Ohtake, Satoshi, Fujiwara, HideoNara Institute of Science and Technology2009-09Information Science Technical ReportTR2009004
Available onlineOther Libraries in Japan
  • Author HeadingIwata, Hiroshi Ohtake, Satoshi Fujiwara, Hideo

Efficient Mutual Exclusion Algorithm for High System Congestion

Efficient Mutual Exclusion Algorithm for High System Congestion
Digital文書・図像類
Suzuki, Tsuyoshi, Inoue, Michiko, Fujiwara, HideoNara Institute of Science and Technology2009-01Information Science Technical ReportTR2009001
Available onlineOther Libraries in Japan
  • Author HeadingSuzuki, Tsuyoshi Inoue, Michiko Fujiwara, Hideo

Over-testing reduction for delay faults through false path exclusion using RTL information

Over-testing reduction for delay faults through false path exclusion using RTL information
Digital文書・図像類
Yoshikawa, Yuki, Ohtake, Satoshi, Fujiwara, HideoNara Institute of Science and Technology2007-06Information Science Technical ReportTR2007012
Available onlineOther Libraries in Japan
  • Author HeadingYoshikawa, Yuki Ohtake, Satoshi Fujiwara, Hideo

気体電子回折によるトリメチルアミンとプロピレンイミンの熱分解生成物の分子構造決定

気体電子回折によるトリメチルアミンとプロピレンイミンの熱分解生成物の分子構造決定
PaperDigital博士論文障害者向け資料あり
藤原英夫 [著]<UT51-95-L280>
Available onlineNational Diet Library

An SoC test scheduling algorithm using reconfigurable union wrappers

An SoC test scheduling algorithm using reconfigurable union wrappers
Digital文書・図像類
Yoneda, Tomokazu, Imanishi, Masahiro, Fujiwara, HideoNara Institute of Science and Technology2006-09Information Science Technical ReportTR2006006
Available onlineOther Libraries in Japan
  • Author HeadingYoneda, Tomokazu Imanishi, Masahiro Fujiwara, Hideo

Classification of sequential circuits based on acyclic test generation complexity

Classification of sequential circuits based on acyclic test generation complexity
Digital文書・図像類
Ooi, Chia Yee, Fujiwara, HideoNara Institute of Science and Technology2006-07Information Science Technical ReportTR2006004
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Fujiwara, Hideo

A new class of sequential circuits with acyclic test generation complexity

A new class of sequential circuits with acyclic test generation complexity
Digital文書・図像類
Ooi, Chia Yee, Fujiwara, HideoNara Institute of Science and Technology2006-05Information Science Technical ReportTR2006003
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Fujiwara, Hideo

An approach to reduce over-testing of path delay faults in data paths using RT-level information

An approach to reduce over-testing of path delay faults in data paths using RT-level information
Digital文書・図像類
Yoshikawa, Yuki, Ohtake, Satoshi, Fujiwara, HideoNara Institute of Science and Technology2006-02Information Science Technical ReportTR2006001
Available onlineOther Libraries in Japan
  • Author HeadingYoshikawa, Yuki Ohtake, Satoshi Fujiwara, Hideo

Efficient and effective test program generation for software-based self-test of pipelined processors

Efficient and effective test program generation for software-based self-test of pipelined processors
Digital文書・図像類
Inoue, Michiko, Nakazato, Masato, Yokoyama, Shinya, Kambe, Kazuko, Fujiwara, HideoNara Institute of Science and Technology2006-08Information Science Technical ReportTR2006005
Available onlineOther Libraries in Japan
  • Author HeadingInoue, Michiko Nakazato, Masato Yokoyama, Shinya Kambe, Kazuko Fujiwara, Hideo

Power-constrained test scheduling for multi-clock domain SoCs

Power-constrained test scheduling for multi-clock domain SoCs
Digital文書・図像類
Yoneda, Tomokazu, Masuda, Kimihiko, Fujiwara, HideoNara Institute of Science and Technology2005-06Information Science Technical ReportTR2005004
Available onlineOther Libraries in Japan
  • Author HeadingYoneda, Tomokazu Masuda, Kimihiko Fujiwara, Hideo

Test generation complexity for stuck-at and path delay faults based on tau[k] - notation

Test generation complexity for stuck-at and path delay faults based on tau[k] - notation
Digital文書・図像類
Ooi, Chia Yee, Clouqueur, Thomas, Fujiwara, HideoNara Institute of Science and Technology2005-05Information Science Technical ReportTR2005003
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Clouqueur, Thomas Fujiwara, Hideo

マクロ金融経済学の転換と証券市場 : 信用と貨幣の創造

マクロ金融経済学の転換と証券市場 : 信用と貨幣の創造
Paper図書
藤原秀夫 著晃洋書房2018.11<DF111-L103>
National Diet LibraryOther Libraries in Japan

Design for testability based on single-port-change delay testing for data paths

Design for testability based on single-port-change delay testing for data paths
Digital文書・図像類
Yoshikawa, Yuki, Ohtake, Satoshi, Inoue, Michiko, Fujiwara, HideoNara Institute of Science and Technology2005-08Information Science Technical ReportTR2005005
Available onlineOther Libraries in Japan
  • Author HeadingYoshikawa, Yuki Ohtake, Satoshi Inoue, Michiko Fujiwara, Hideo

Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generation

Acceleration of transition test generation for acyclic sewuential circuits utilizing constrained combinational stuck-at test generation
Digital文書・図像類
Iwagaki, Tsuyoshi, Ohtake, Satoshi, Fujiwara, HideoNara Institute of Science and Technology2004-12Information Science Technical ReportTR2004009
Available onlineOther Libraries in Japan
  • Author HeadingIwagaki, Tsuyoshi Ohtake, Satoshi Fujiwara, Hideo

戦後家庭教育文献叢書 第8巻

戦後家庭教育文献叢書 第8巻
Paper図書
クレス出版1996.6<EF34-G95>
National Diet LibraryOther Libraries in Japan

Some tau-equivalent classes of sequential circuits

Some tau-equivalent classes of sequential circuits
Digital文書・図像類
Ooi, Chia Yee, Fujiwara, HideoNara Institute of Science and Technology2004-06Information Science Technical ReportTR2004002
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Fujiwara, Hideo

Software-based delay fault self-testing of pipelined processor cores

Software-based delay fault self-testing of pipelined processor cores
Digital文書・図像類
Singh, Virendra, Inoue, Michiko, Saluja, Kewal K., Fujiwara, HideoNara Institute of Science and Technology2004-09Information Science Technical ReportTR2004006
Available onlineOther Libraries in Japan
  • Author HeadingSingh, Virendra Inoue, Michiko Saluja, Kewal K. Fujiwara, Hideo

Classification of sequential circuits based on combinational test generation complexity

Classification of sequential circuits based on combinational test generation complexity
Digital文書・図像類
Ooi, Chia Yee, Fujiwara, HideoNara Institute of Science and Technology2004-01Information Science Technical ReportTR2004001
Available onlineOther Libraries in Japan
  • Author HeadingOoi, Chia Yee Fujiwara, Hideo